The present invention relates generally to an SOI type semiconductor device and a manufacturing method therefor, and more particularly to a bipolar transistor, a Bi-MOS device and a manufacturing method therefor.
A bipolar transistor having an SOI structure has been proposed to aim at a reduction in junction capacitance Cjs, an improvement in .alpha.-ray resistance, etc.
On the other hand, a vertical bipolar transistor having an improved operating performance has also been proposed. Such a vertical bipolar transistor can make it possible to reduce a base width.
In forming an NPN bipolar transistor having a maximum cut-off frequency of about 32 GHz, for example, it must be formed as a vertical NPN bipolar transistor.
An example of such a vertical NPN bipolar transistor employing an SOI substrate will be described with reference to FIG. 1.
Referring to FIG. 1, reference numeral 1 designates an SOI substrate having an n-type silicon thin film 2. Element isolating regions 3 and 4 are formed in the n-type silicon thin film 2.
An n.sup.+ buried diffusion layer 5 is formed in a lower layer of the n-type silicon thin film 2. An element isolating region 6 is formed in an upper layer of the n-type silicon thin film 2 at a portion thereof above the n.sup.+ buried diffusion layer 5.
A p.sup.+ base region 7 is formed on an upper surface of the n-type silicon thin film 2 between the element isolating regions 3 and 6. The p.sup.+ base region 7 is formed from a p.sup.+ epitaxial silicon thin film. An n.sup.+ collector leading region 8 is formed in the upper layer of the n-type silicon thin film 2 between the element isolating regions 6 and 4 so as to be connected with the n.sup.+ buried diffusion layer 5.
A p.sup.+ polysilicon film 9 is formed on the p.sup.+ base region 7.
A first insulating film 10 is formed on the whole upper surface so as to cover the p.sup.+ polysilicon film 9.
A contact hole 11 is formed through the first insulating film 10 and the p.sup.+ polysilicon film 9 on the p.sup.+ base region 7. A side wall insulating film 12 is formed on a side wall of the contact hole 11. An n.sup.+ emitter region 13 is formed along a side wall of the side wall insulating film 12 so as to be connected with the p.sup.+ base region 7.
A contact hole 14 is formed through the first insulating film 10 on the n.sup.+ collector leading region 8. An n.sup.+ collector leading electrode 15 is formed in the contact hole 14 so as to be connected with the n.sup.+ collector leading region 8.
A second insulating film 16 is formed on the first insulating film 10 so as to overlap the n.sup.+ emitter region 13 and the n.sup.+ collector leading electrode 15. A contact hole 17 is formed through the first and second insulating films 10 and 16 on the p.sup.+ polysilicon film 9. A contact hole 18 is formed through the second insulating film 16 on the n.sup.+ emitter region 13. A contact hole 19 is formed through the second insulating film 16 on the n.sup.+ collector leading electrode 15.
A base electrode 20 is formed in the contact hole 17 so as to be connected with the p.sup.+ polysilicon film 9. An emitter electrode 21 is formed in the contact hole 18 so as to be connected with the n.sup.+ emitter region 13. A collector electrode 22 is formed in the contact hole 19 so as to be connected with the n.sup.+ collector leading electrode 15.
Thus, the vertical NPN bipolar transistor has the above construction.
In the vertical NPN bipolar transistor, the silicon thin film of the SOI substrate is required to have a thickness of about 1.0 .mu.m. Accordingly, in the case of using a thin film MOS FET wherein a silicon thin film has a thickness of about 0.15 .mu.m in combination with the above vertical NPN bipolar transistor, it is difficult to mount both the above thin film MOS FET and the above vertical NPN bipolar transistor on the same silicon thin film of the SOI substrate.
Further, in the vertical bipolar transistor, it is necessary to form the buried diffusion layer, so as to reduce a parasitic resistance. The formation of the buried diffusion layer causes enlargement of a bipolar transistor forming area, resulting in difficulty of high integration.
Under the above circumstances, there has been proposed a lateral bipolar transistor having an SOI structure which can make it possible to reduce a base width.
An SOI type lateral bipolar transistor in the prior art will be described with reference to FIG. 2.
Referring to FIG. 2, reference numeral 30 generally designates a lateral bipolar transistor. A transistor forming region 32 of monosilicon is formed on an insulating substrate (e.g., silicon oxide substrate) 31. Element isolating regions 33 and 34 are also formed on the insulating substrate 31 on both sides of the transistor forming region 32.
An emitter region 35, a base region 36, a collector region 37 and a high-concentration impurity region (which will be hereinafter referred to as a collector contact region) 38 for contact formation are formed in the transistor forming region 32 in this order from the element isolating region 33 side. The collector region 37 is formed as a portion of the transistor forming region 32.
An emitter leading electrode 40 is formed on the transistor forming region 32 so as to be connected with the emitter region 35 through a first silicon oxide film 39. A collector leading electrode 41 is formed on the transistor forming region 32 so as to be connected with the collector contact region 38 through the first silicon oxide film 39. A second silicon oxide film 42 is formed so as to cover the first silicon oxide film 39, the emitter leading electrode 40 and the collector leading electrode 41. A base contact portion 43 is formed between the emitter leading electrode 40 and the collector leading electrode 41 and through the second silicon oxide film 42. A side wall insulating film 44 is formed on a side wall of the base contact portion 43. A base leading electrode 45 is formed in the base contact portion 43 so as to be connected with the base region 36.
Thus, the lateral bipolar transistor 30 has the above construction.
A manufacturing method for such a lateral bipolar transistor will be described with reference to FIGS. 3A to 3E.
In the first step shown in FIG. 3A, an insulating substrate 51 and a monosilicon substrate 71 are bonded together by a usual wafer bonding method. Then, the monosilicon substrate 71 is polished to remove a portion shown by a two-dot chain line and thereby form a monosilicon region 72 on the insulating substrate 51.
In the second step shown in FIG. 3B, element isolating regions 53 and 54 are formed in the monosilicon region 72 by a LOCOS process. Thus, a portion of the monosilicon region 72 between the element isolating regions 53 and 54 is formed as a transistor forming region 52.
In the third step shown in FIG. 3C, a first silicon oxide film 59 is formed on the whole upper surface of the transistor forming region 52 and the element isolating regions 53 and 54 by a CVD process. Then, a portion of the first silicon oxide film 59 shown by a two-dot chain line is removed by a photolithography and etching process to form grooves 73 and 74.
In the fourth step shown in FIG. 3D, a polysilicon film 75 containing a first conduction type of impurity is formed in the grooves 73 and 74 and on the upper surface of the first silicon oxide film 59 by a CVD process. Then, a polysilicon region 76 is formed from the polysilicon film 75 by a photolithography and etching process. Then, a second silicon oxide film 62 is formed on the whole upper surface of the polysilicon region 76 and the first silicon oxide film 59 by a CVD process.
In the fifth step shown in FIG. 3E, a base contact portion 63 is formed through the second silicon oxide film 62 and the polysilicon region 76 by a photolithography and etching process. At the same time, an emitter leading electrode 60 and a collector leading electrode 61 are formed from the polysilicon region 76.
Then, a third silicon oxide film 77 is formed in the base contact portion 63 and on the upper surface of the second silicon oxide film 62, and is then etched back to form a side wall insulating film 64 on a side wall of the base contact portion 63 from the third silicon oxide film 77.
Then, a polysilicon film 78 containing a second conduction type of impurity is formed on the upper surface of the second silicon oxide film 62 so as to fill the base contact portion 63. Then, a portion of the polysilicon film 78 shown by a two-dot chain line is removed by a photolithography and etching process to form a base leading electrode 65 from the polysilicon film 78.
Then, the first conduction type of impurity contained in the emitter leading electrode 60 and the collector leading electrode 61 is diffused into the transistor forming region 52 by a thermal diffusion process to form an emitter region 55 and a collector contact region 58 in the transistor forming region 52. Similarly, the second conduction type of impurity contained in the base leading electrode 65 is diffused into the transistor forming region 52 by a thermal diffusion process to form a base region 56 in the transistor forming region 52. Further, the remaining portion of the transistor forming region 52 where no impurity has been diffused between the base region 56 and the collector region 58 is formed as a collector region 57.
In this way, a lateral bipolar transistor 50 shown in FIG. 3E is formed.
However, in the above lateral bipolar transistor, the base region is formed by diffusing the second conduction type of impurity from the base leading electrode into the transistor forming region. Therefore, the width of the base region is defined by the junction width of the base leading electrode and the transistor forming region between the opposed portions of the side wall insulating film. Accordingly, the width of the base region is fluctuated with variations in the width of the side wall insulating film, resulting in variations in electrical characteristics such as current amplification factor h.sub.FE and cut-off frequency f.sub.T to cause a reduction in reliability.
Recent LSIs having been practically applied are demanded to have a larger scale and higher performance. In particular, there has been proposed a Bi-CMOS device including a CMOS transistor allowing low power consumption and high integration and a bipolar transistor superior in high-speed operability, both being mounted on a common substrate.
However, in a field effect MOS transistor (MOS FET) having a very minute construction such that a gate length is in a subhalf micron level, there is a problem that a subthreshold characteristic is deteriorated because of a short channel effect. As measures for solving the problem, there has been proposed a MOS transistor having a complete depletion type thin film SOI structure.
In such a MOS transistor having a complete depletion type thin film SOI structure, the thickness of a thin silicon film having an SOI structure is set to be equal to or smaller than the thickness of a depletion layer to thereby terminate a drain electric field at a gate and prevent that the drain electric field will reach a source region. Therefore, the deterioration in the subthreshold characteristic due to the short channel effect can be suppressed.
Furthermore, in a MOS FET having a thin film SOI structure, bending of a band in a thin silicon film upon formation of an inversion layer is suppressed to reduce surface scattering of carriers. Therefore, a carrier mobility can be increased.
In particular, a MOS FET having a so-called double gate structure such that a thin silicon film of an SOI is sandwiched between two gate electrodes has an advantage that a transconductance gm can be enlarged more than that in a MOS FET having a single gate structure such that a single gate is formed on a thin silicon film of an SOI substrate.
FIG. 4 shows such a double gate type MOS FET in the prior art.
Referring to FIG. 4, reference numeral 80 generally designates a double gate MOS FET. An insulating layer 82 of silicon oxide is formed on a substrate 81. A thin silicon film 83 is formed in an upper layer of the insulating layer 82. A channel forming region 84 is formed in the thin silicon film 83. A source region 85 is formed in the thin silicon film 83 on one side of the channel forming region 84, and a drain region 86 is formed in the thin silicon film 83 on the other side of the channel forming region 84. A back gate electrode 88 is formed under the channel forming region 84 with a back gate insulating film 87 interposed therebetween. A front gate electrode 90 is formed over the channel forming region 84 with a front gate insulating film 89 interposed therebetween.
An insulating film 91 is formed on the whole upper surface of the insulating layer 82 so as to cover the thin silicon film 83 and the front gate electrode 90. Contact holes 92 and 93 are formed through the insulating film 91 on the source region 85 and the drain region 86, respectively. Electrodes 94 and 95 are formed in the contact holes 92 and 93 so as to be connected with the source region 85 and the drain region 86, respectively.
Thus, formed is the MOS FET 80 having a double gate structure such that the thin silicon film 83 of the SOI substrate is sandwiched between the back gate electrode 88 and the front gate electrode 90.
FIGS. 5 and 6 show a conventional bipolar transistor which can be mounted in combination with the MOS FET 80 mentioned above on the same SOI substrate.
Referring to FIG. 5, reference numeral 100 generally designates a lateral NPN bipolar transistor. An SOI substrate 101 is constituted of an insulating layer 102 and an n-type thin silicon film 103. Element isolating regions 104 and 105 are formed in the n-type thin silicon film 103. A silicon oxide film 106 is formed in an upper layer of the n-type thin silicon film 103 at a portion thereof adjacent to the element isolating region 104. An n.sup.+ collector electrode 107 is formed on an upper surface of the n-type thin silicon film 103 so as to overlap a portion of the silicon oxide film 106. A side wall insulating film 108 is formed on a side wall of the n.sup.+ collector electrode 107 on the element isolating region 104 side. An n.sup.+ emitter region 109 is formed in the n-type thin silicon film 103 at the portion thereof adjacent to the element isolating region 104. A p-type base region 110 is formed in the n-type thin silicon film 103 at a portion thereof adjacent to the n.sup.+ emitter region 109 under the side wall insulating film 108.
As shown in FIG. 6, p-type base contact portions 111 and 112 are connected with the p-type base region 110. Each of the p-type base contact portions 111 and 112 is formed as a diffusion layer in which a p-type impurity is diffused as similar to the p-type base region 110.
A remaining portion of the n-type thin silicon film 103 adjacent to the element isolating region 105 is formed as an n-type collector region 113.
Thus, the lateral NPN bipolar transistor 100 has the above construction.
The lateral NPN bipolar transistor 100 mentioned above is formed in the n-type thin silicon film 103 of the SOI substrate 101. Accordingly, the lateral NPN bipolar transistor 100 shown in FIGS. 5 and 6 and the MOS FET 80 shown in FIG. 4 can be mounted on the same SOI substrate.
However, in the lateral NPN bipolar transistor as mentioned above, the width of the side wall insulating film becomes the width of the base region. Therefore, if the width of the base region is equal to or smaller than 100 nm, the direct contact with the base region cannot be made, so that the contact with the base region should be located apart from the base region. As a result, a parasitic capacitance is increased to reduce electrical characteristics. Further, since the base region becomes large in size, an element area is increased to cause a bottleneck to high integration.
FIG. 7 shows another example of a double gate type MOS FET employing a thin film SOI. As shown in FIG. 7, an insulating layer 123 is formed on a base substrate 120 by a known bonding technique, and a thin bulk silicon film 123a is formed in an upper layer of the insulating layer 123. A front gate electrode 121a and a back gate electrode 121b are formed so as to interpose the silicon film 123a therebetween. A source region 122a and a drain region 122b are formed in the silicon film 123a on both sides of the front gate electrode 121a.
FIGS. 8A to 8F show a manufacturing process for the double gate structure of the MOS FET mentioned above.
As shown in FIG. 8A, field oxide films 131 and an insulating film (CVD oxide film) 132 are formed on a silicon substrate 130, and then the insulating film 132 is etched to form a back gate region.
As shown in FIG. 8B, a back gate oxide film 132a is formed in the back gate region, and then a polysilicon film 133 as a back gate electrode is formed on the back gate oxide film 132a.
As shown in FIG. 8C, an insulating film (CVD oxide film) 134 is formed on the insulating layer 132, and then an upper surface of the insulating film 134 is flattened by polishing.
As shown in FIG. 8D, a base substrate 130' having an oxide film 132' is bonded to the insulating film 134 of the silicon substrate 130 by a thermal bonding method utilizing vacuum electrostatic adsorption.
As shown in FIG. 8E (vertically inverted from FIG. 8D), the silicon substrate 130 is partially removed from its back surface (i.e., the lower surface as viewed in FIG. 8D) by grinding and selective polishing with use of the field oxide films 131 as a polish stopper. As a result, a thin silicon film (SOI) 130a is residually formed between the field oxide films 131.
As shown in FIG. 8F, a front gate electrode 135 is formed on the thin silicon film 130a through a front gate insulating film in a known manner.
As described above, such a double gate type MOS FET employing a thin film SOI is considered to be primarily applied as a MOS FET in a Bi-CMOS LSI of a subhalf micron class. Accordingly, it has been greatly demanded to realize a bipolar transistor which can suitably match the double gate type MOS FET.
In view of the above demand, there has already been proposed a high-performance bipolar transistor having an SOI structure and a manufacturing method therefor which can well match the double gate type MOS FET.
In this proposed bipolar transistor, an emitter region and a base region are formed by double diffusion from a common polysilicon film. Further, the contact with the base region (intrinsic base) is made on a bottom surface of the base region, so that a small base width to be determined at a side portion of the base region can be realized. Further, a reduction in electrical characteristics and degree of integration due to separation between the base region and the base contact can be prevented.
A manufacturing method for such a thin film SOI type bipolar transistor and a double gate thin film SOI type MOS FET to be mounted on a common SOI substrate will be described with reference to FIGS. 9A to 9E.
In the first step shown in FIG. 9A, a silicon substrate 140 with a crystal orientation of &lt;100&gt; is oxidized by LOCOS to form field oxide films (SiO.sub.2) 141 for element isolation. These field oxide films 141 also serve as a polish stopper in a wafer polishing step to be hereinafter described.
The thickness of a thin silicon layer constituting a thin film SOI substrate to be formed later is about 1/2 of the thickness of each field oxide film. For example, when the thickness of each field oxide film is set to 200 nm, the thickness of the thin silicon layer becomes about 100 nm.
Then, a back gate oxide film 142a is formed on the upper surface of the silicon substrate 140, and then a polysilicon film 143a is formed on the back gate oxide film 142a. Then, the polysilicon film 143a and the back gate oxide film 142a on a bipolar transistor forming region only are removed.
Then, an insulating layer (SiO.sub.2) 142 is formed by CVD on the upper surface of the silicon substrate 140, and then the upper surface of the insulating layer 142 is flattened by etch-back after resist coating. The thickness of the insulating layer 142 after flattened is about 100-200 nm.
Then, grooves 151 and 152 are formed through the insulating layer 142 at the bipolar transistor forming region and a MOS FET forming region, respectively.
Then, side wall films (SiO.sub.2) 142' are formed on side walls of the grooves 151 and 152 by CVD and RIE. These side wall films 142' serve to allow for alignment between a base region (intrinsic base) and a base contact of the bipolar transistor and between a back gate electrode and a gate electrode of the MOS FET.
In the second step shown in FIG. 9B, a polysilicon film 143b is formed by CVD on the upper surface of the insulating layer 142 so as to fill the grooves 151 and 152, and then the polysilicon film 143b is removed by etch-back after resist coating to form a base leading electrode of the bipolar transistor and a back gate electrode of the MOS FET in the grooves 151 and 152, respectively.
The formation of the base leading electrode and the back gate electrode may be effected by selective CVD. The thickness of each polysilicon film 143b formed in the grooves 151 and 152 is about 50-100 nm.
Then, as required, a suitable conduction type of impurity is introduced into the polysilicon film 143b and diffused therein by ion implantation and annealing. For example, when forming an NPN bipolar transistor, the polysilicon film 143b in the groove 151 is doped with a p-type impurity; when forming a PMOS FET, the polysilicon film 143b in the groove 152 is doped with a p-type impurity; and when forming an NMOS FET, the polysilicon film 143b in the groove 152 is doped with an n-type impurity.
Then, tungsten (W) electrodes 144a are formed in the grooves 151 and 152 by selective CVD, so as to reduce wiring resistances of the base leading electrode and the back gate electrode. Then, an insulating film (SiO.sub.2) 144 is formed by CVD on the insulating film 142.
In the third step shown in FIG. 9C (vertically inverted from FIG. 9B), a silicon substrate 140' as a back wafer is bonded to a back surface of the insulating film 144, and then the silicon substrate 140 is polished from its upper surface as viewed in FIG. 9C until the field oxide films 141 are exposed, so that thin silicon layers 140a as SOI regions are residually formed between the field oxide films 141.
In the fourth step shown in FIG. 9D, a gate oxide film 142b is formed on the thin silicon layers 140a by thermal oxidation, and then a polysilicon film 143c is formed on the gate oxide film 142b by CVD. Then, the polysilicon film 143c and the gate oxide film 142b are etched by RIE with a resist mask covering an emitter and base region forming area and a MOS FET forming area.
Then, a polysilicon film 143d is formed so as to fully cover the polysilicon film 143c patterned above. The polysilicon films 143c and 143d function as a collector leading electrode of the bipolar transistor and a gate electrode of the MOS FET. Then, as required, a suitable conduction type of impurity is introduced into the polysilicon film 143d and diffused therein by ion implantation and annealing. For example, when forming an NPN bipolar transistor, the polysilicon film 143d for the collector leading electrode is doped with an n-type impurity; when forming a PMOS FET, the polysilicon film 143d for the gate electrode is doped with a p-type impurity; and when forming an NMOS FET, the polysilicon film 143d is doped with an n-type impurity.
Then, an insulating film (SiO.sub.2) 145 is formed by CVD on the polysilicon film 143d. Then, a resist mask 146 is formed on the insulating film 145 so as to cover the bipolar transistor forming region and a gate electrode forming region.
In the fifth step shown in FIG. 9E, the insulating film 145 and the polysilicon film 143d are etched by RIE with the resist mask 146.
Then, the insulating film 145, the polysilicon film 143d, the polysilicon film 143c and the gate oxide film 142b existing on the bipolar transistor forming region are etched by RIE to form an emitter contact hole.
Then, side wall insulating films (SiO.sub.2) 147 are formed by CVD and RIE on side walls of the emitter contact hole and the gate electrode. In the case of making an LDD structure in the MOS FET, ion implantation for forming an LDD is performed before forming the side wall insulating films 147. In this case, the side wall insulating film 147 on the side wall of the gate electrode also serves as an LDD spacer.
Then, a polysilicon film 143e is formed on the whole upper surface. The polysilicon film 143e on the bipolar transistor forming region functions as an emitter leading electrode, and the polysilicon film 143e on the MOS FET forming region functions as source and drain leading electrodes.
Then, in the case of an NPN bipolar transistor, a p-type impurity such as boron ions (B.sup.+) is implanted into the polysilicon film 143e on the bipolar transistor forming region, and then annealing is performed to form a p-type base region in the thin silicon layer 140a. Then, an n-type impurity such as arsenic ions (As.sup.+) is implanted into the polysilicon film 143e on the bipolar transistor forming region, and then annealing is performed to form an n.sup.+ emitter region in the thin silicon layer 140a on the p-type base region. Further, in the case of a PMOS FET, a p-type impurity such as boron ions (B.sup.+) is implanted into the polysilicon film 143e on the MOS FET forming region, and then annealing is performed to form p.sup.+ source and drain regions in the thin silicon layer 140a, while in the case of an NMOS FET, an n-type impurity such as arsenic ions (As.sup.+) is implanted into the polysilicon film 143e on the MOS FET forming region, and then annealing is performed to form n.sup.+ source and drain regions in the thin silicon layer 140 a.
Then, the polysilicon film 143e is etched to form the emitter leading electrode and the source and drain leading electrodes.
Then, although not shown, an insulating film (SiO.sub.2) is formed on the whole upper surface, and then contact holes are formed through the insulating film so as to expose the emitter leading electrode, the collector leading electrode, the source leading electrode and the drain leading electrode. Then, metal electrodes are formed in the contact holes from Ti/TiN/Al-Si, polysilicon/tungsten silicide, etc.
In this manner, the thin film SOI type bipolar transistor and the double gate thin film SOI type MOS FET are simultaneously formed on the same substrate. This bipolar transistor is constituted of an intrinsic region and a minimum contact region, and is substantially surrounded by an insulator, thus effecting high performance and high integration.
According to this technique, the base contact is formed just under the base region to thereby form a high-performance lateral bipolar transistor. Further, the polysilicon film for forming the base leading electrode of the bipolar transistor and the polysilicon film for forming the back gate electrode of the MOS FET are simultaneously buried in the same substrate, thus easily simultaneously forming the high-performance thin film SOI type bipolar transistor and the double gate thin film SOI type MOS FET on the same substrate.
However, this technique still has the following problem. That is, while the base contact is formed from the polysilicon film buried just under the base region, there is a possibility that the high-concentration impurity introduced into the polysilicon film forming the base contact is undesirably diffused into the base region by a thermal process upon forming elements.
This problem is considered to be due to the fact that:
(1) the base contact of the polysilicon film is located close to the base region (intrinsic base); and
(2) a diffusion coefficient of the impurity in the polysilicon film is large.
The diffusion of the high-concentration impurity into the base region causes an increase in base Gummel Number, which will in turn cause various adverse effects on characteristics such as a fluctuation in Hfe, a reduction in Vebo and an increase in Cje.